As high‑speed interfaces push signal integrity to its limits, chip‑level verification is no longer enough. This case study shows how Qualitas Semiconductor transformed its PHY IP development by shifting to system‑level, measurement‑driven validation. Using Anritsu’s ShockLine™ MS46524B Vector Network Analyzer, Qualitas uncovered real‑world interconnect effects that simulations often miss, improving design quality, shortening development cycles, and strengthening customer confidence. Read on to see how a modern verification strategy is becoming a decisive competitive advantage.
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17:58Validation examples using the Sequence Editor function on the Signal Quality Analyzer-R MP1900A
29:22PCI-SIG is finalizing the PCIe 6.0 standard to support the spread of AI and machine learning for DCI. PCIe 6.0 extends the PCIe 5.0 transmission speed from 32 to 64 GT/s by changing the modulation met
Anritsu characterizes PCIe 64 GT/s intra-pair skew, providing BER insights to guide PAM4 tolerance, simulation correlation, and next-gen PCIe design.
14:47Learn how to perform PCIe® 6.0 Rx and Tx LEQ Tests with Return Path Optimization and FEC debugging.
Learn how Anritsu evaluates intra-pair skew in PCIe & USB interfaces, its effect on BER, and methods to ensure high-speed digital signal quality.
Discover how Optical Transport Networks (OTNs) enable high-speed, low-latency, and scalable data transmission for AI, cloud, and IoT—powering next-gen networks with advanced error correction.
45:20PCI Express® (PCIe®) technology has long met the bandwidth and reliability demands of traditional high-performance data center computing, which is why it is being leveraged by the automobile industry
As a developer of automotive solutions leveraging PCIe technology, it is critical that you have the right technology to ensure your solutions are compliant.
Explore key signal integrity concepts like COM, eye patterns, crosstalk, and skew to tackle measurement challenges in today’s high-speed digital and RF systems.
This post explores why skew is becoming a bigger issue than ever, how it affects signal integrity, and how to measure and manage it with confidence.
Get expert insights on testing strategies to accelerate design cycles and keep pace with advances in embedded systems, high-speed communication, and compact, high-speed electronics.
27:23This webinar focuses on Ethernet standard and Ethernet test of 400/800G including PAM4
The sampling oscilloscope is an ideal instrument for analyzing the eye pattern of these digital signals.
36:20PCIe 6.0 introduces Flow Control Unit (FLIT) encoding to allow forward error correction (FEC) on fixed-size packets. Stress testing PCIe hardware includes addressing this new protocol approach.
Read this Design World article to learn about the evolution of PCIe and the specifics of PCIe 6.0 as compared to previous specifications including the integration of PAM4 technology and FLIT encoding
44:41Watch this webinar to learn about Automotive technology and testing in Telematics, Infotainment and ADAS, including 5G/cellular, server applications, and more
This paper outlines the enhanced PCIe 6.0 technologies, such as PAM4, Forward Error Correction (FEC) and link equalization