As high‑speed interfaces push signal integrity to its limits, chip‑level verification is no longer enough. This case study shows how Qualitas Semiconductor transformed its PHY IP development by shifting to system‑level, measurement‑driven validation. Using Anritsu’s ShockLine™ MS46524B Vector Network Analyzer, Qualitas uncovered real‑world interconnect effects that simulations often miss, improving design quality, shortening development cycles, and strengthening customer confidence. Read on to see how a modern verification strategy is becoming a decisive competitive advantage.
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29:22PCI-SIG is finalizing the PCIe 6.0 standard to support the spread of AI and machine learning for DCI. PCIe 6.0 extends the PCIe 5.0 transmission speed from 32 to 64 GT/s by changing the modulation met
17:58Validation examples using the Sequence Editor function on the Signal Quality Analyzer-R MP1900A
Explore key signal integrity concepts like COM, eye patterns, crosstalk, and skew to tackle measurement challenges in today’s high-speed digital and RF systems.
Anritsu characterizes PCIe 64 GT/s intra-pair skew, providing BER insights to guide PAM4 tolerance, simulation correlation, and next-gen PCIe design.
Learn how Anritsu evaluates intra-pair skew in PCIe & USB interfaces, its effect on BER, and methods to ensure high-speed digital signal quality.
Discover how Optical Transport Networks (OTNs) enable high-speed, low-latency, and scalable data transmission for AI, cloud, and IoT—powering next-gen networks with advanced error correction.
45:20PCI Express® (PCIe®) technology has long met the bandwidth and reliability demands of traditional high-performance data center computing, which is why it is being leveraged by the automobile industry
This post explores why skew is becoming a bigger issue than ever, how it affects signal integrity, and how to measure and manage it with confidence.
27:23This webinar focuses on Ethernet standard and Ethernet test of 400/800G including PAM4
2:30This DesignCon 2026 show‑floor video demonstrates a live PCIe Gen 6 TX/RX validation workflow using the MP1900 platform.
The sampling oscilloscope is an ideal instrument for analyzing the eye pattern of these digital signals.
36:20PCIe 6.0 introduces Flow Control Unit (FLIT) encoding to allow forward error correction (FEC) on fixed-size packets. Stress testing PCIe hardware includes addressing this new protocol approach.
This paper outlines the enhanced PCIe 6.0 technologies, such as PAM4, Forward Error Correction (FEC) and link equalization
Lightwave’s latest eBook explores innovation in optical components, covering PCIe, linear pluggable optics (LPO), and AI-driven growth in 800G Ethernet optics.
28:09High-speed and large-capacity transmission standards using PAM4 signaling, such as 400 GbE, stipulate the use of Forward Error Correction (FEC) to assure transmission quality
This application note explains the Signal Quality Analyzer-R (SQA-R) MP1900A FEC Solution and describes a concrete example of the FEC Rx test using the MU196040B PAM4 ED FEC Symbol Capture function.
59:19Watch this demonstration of PAM4 Jitter Tolerance test and FEC burst error analysis using Anritsu’s BERT Signal Quality Analyzer-R MP1900A.