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PCIe 6.0 LEQ Test Solution and Unique Intra-Pair Skew Resolution at 64GT/s Speed

In high-speed backplanes and interconnects, the intra-lane skew of the differential signal (P/N) becomes one of the significant factors in reducing the eye margin. Due to the small phase margin of the PAM4 signal, it has a significant impact on causing errors in data transmission. In this webinar hosted by the Optical Communications Technical Group, Hiroshi Goto will quantify the intra-lane skew versus BER (Bit Error Rate) at 32Gbaud PAM4 signal (PCIe 6.0) with the repeatable skew control. Goto’s presentation will show a novel and reliable method for introducing granular intra-pair skew into the channel and measuring the impact of BER.

What You Will Learn:

  • How to quantify the intra-lane skew versus BER (Bit Error Rate) at 32Gbaud PAM4 signal (PCIe 6.0) with Anritsu’s test solution 

A novel method for introducing granular intra-pair skew into the channel

BERT - Bit Error Rate Tester | Anritsu America

Signal Quality Analyzer-R MP1900A | Anritsu America

Previous Video
Unleash PCIe 6.0 USB Debugging and Validation
Unleash PCIe 6.0 USB Debugging and Validation

Sequence Editor function of the Signal Quality Analyzer-R MP1900A

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Empirical BER Characterization of Intra-Pair Skew for PCIe at 64/GTs
Empirical BER Characterization of Intra-Pair Skew for PCIe at 64/GTs

Anritsu characterizes PCIe 64 GT/s intra-pair skew, providing BER insights to guide PAM4 tolerance, simulat...