Industry-leading test solutions for your high-speed digital designs and communications
PCIe 5.0 SerDes Test and Analysis
This paper examines the crucial PCIe 5.0 serializer/deserializer (SerDes) tests.
52:17PCIe® 5.0: Solving 32GTs Receiver Compliance and Validation Challenges
This webinar will provide an overview of the methods for solving some of the new test and measurement receiver challenges for PCIE® 5.0 at 32.0 GT/s.
High Speed Data Transmission and Test
This eBook provides guidance on what to consider when developing a high-speed data transmission product or system and the associated test concerns.
1:02:57PCIe® 5.0: Solving 32 GT/s Receiver Compliance & Validation Challenges
This webinar will provide an overview of the methods for solving some of the new test and measurement receiver challenges for PCIE® 5.0 at 32.0 GT/s.
45:20PCIe® Technology in Advanced Automotive Designs
PCI Express® (PCIe®) technology has long met the bandwidth and reliability demands of traditional high-performance data center computing, which is why it is being leveraged by the automobile industry
Tackling Verification Challenges for PCIe 5.0
PCIe 5.0 works at 32 GT/s data rate per lane, double its predecessor
PCIe® Receiver Test by MP1900A Series
As a developer of automotive solutions leveraging PCIe technology, it is critical that you have the right technology to ensure your solutions are compliant.
27:23PAM4 BER and JTOL Test Solutions for PCIE 6 and BEYOND
This webinar focuses on Ethernet standard and Ethernet test of 400/800G including PAM4
Basics of Eye Pattern Analysis
The sampling oscilloscope is an ideal instrument for analyzing the eye pattern of these digital signals.
36:20Stress Testing PCIe 6.0 FLIT-based Forward Error Correction
PCIe 6.0 introduces Flow Control Unit (FLIT) encoding to allow forward error correction (FEC) on fixed-size packets. Stress testing PCIe hardware includes addressing this new protocol approach.
What you Need to Know about Error Analysis in PCIe® 6.0 Designs
Read this Design World article to learn about the evolution of PCIe and the specifics of PCIe 6.0 as compared to previous specifications including the integration of PAM4 technology and FLIT encoding
33:21Two-part webinar, focusing on PCIe® 6.0, led by top application engineers from Anritsu and Tektronix
PAM4 BER & JTOL Test Solutions for PCIe 6 & Beyond with Anritsu
All-in-One Futureproof Measurements - MP1900A
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44:41Automotive Testing 2G-6G Challenges & Solutions
Watch this webinar to learn about Automotive technology and testing in Telematics, Infotainment and ADAS, including 5G/cellular, server applications, and more
PCIe® 6.0 Testing for a New Generation
This paper outlines the enhanced PCIe 6.0 technologies, such as PAM4, Forward Error Correction (FEC) and link equalization
28:09400G Post FEC BER and Jitter Tolerance Test for Physical Layer Chip and Module Type
High-speed and large-capacity transmission standards using PAM4 signaling, such as 400 GbE, stipulate the use of Forward Error Correction (FEC) to assure transmission quality
The FEC Pattern Generation MU196020A-042 Quick Start Guide
FEC is a key technology for assuring the quality of large-capacity transmissions, such as 100 and 400 GbE.
Implementing FEC Rx Test using FEC Symbol Capture Function
This application note explains the Signal Quality Analyzer-R (SQA-R) MP1900A FEC Solution and describes a concrete example of the FEC Rx test using the MU196040B PAM4 ED FEC Symbol Capture function.
