Gain a greater understanding of PCIe 5.0 test methodologies, and discuss the anticipated signal integrity-related design and test challenges as the standard moves to PAM-4 signaling, including power dissipation, signal-to-noise ratio, reflections, and cost/performance.
PCI Express® 5.0 operates at 32 GT/s with NRZ signaling, a huge challenge. In 2019, the PCI-SIG® announced that PCIe® 6.0 will double the data rate to 64 GT/s using PAM-4 (Pulse Amplitude Modulation with 4 levels) encoding. With a targeted specification release in 2021, PCIe 6.0 can be expected to present unique challenges for successful design implementation.
- Evolution of PCI Express Technology
- The Challenge of NRZ at 32 GT/s
- Comparison of PCIe Base (ASIC) vs. CEM (system) Testing
- PCIe Transmitter Test Overview
- PCIe Receiver Jitter Tolerance Test Overview
- Link Equalization Test Overview - Transmitter & Receiver
- Transition to PCIe 6.0: 64GT/s PAM4 Design and Test Considerations