PCIe 6.0 introduces Flow Control Unit (FLIT) encoding to allow forward error correction (FEC) on fixed-size packets. Stress testing PCIe hardware includes addressing this new protocol approach. Once FLIT mode is turned on, it will work with any data rate. It improves overall bandwidth and provides low latency, so it is important that hardware is properly tested.
This webinar addresses:
- Correlation between uncorrectable errors and FBER using Flit FEC.
- Flit FEC evaluation analysis method for the Physical Layer under worst-case Rx test conditions.
- Chip and module-level improvement recommendations with respect to uncorrectable error pattern dependency and bit-sequence repeatability.
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