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400G Post FEC BER and Jitter Tolerance Test for Physical Layer Chip and Module Type

High-speed and large-capacity transmission standards using PAM4 signaling, such as 400 GbE, stipulate the use of Forward Error Correction (FEC) to assure transmission quality. Consequently, jitter tolerance tests for SERDES, DSP, and CDR used by transceivers are required at both pre-FEC evaluations of bit error rate performance as well as at correctable/uncorrectable FEC symbol error performance. View this webinar to learn the following:

Latest 400G/800G Market trends
Challenges of high speed PAM4 transmission
Outline of FEC (Forward Error Correction)
Anritsu MP1900A physical layer test solutions with the FEC Analysis
Jitter Tolerance test based on FEC uncorrectable error criteria

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400G Post FEC BER and Jitter Tolerance Test for Physical Layer Chip and Module Type

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