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Tackling Verification Challenges for PCIe 5.0

September 3, 2021

PCIe 5.0 works at 32 GT/s data rate per lane, double its predecessor. It offers many new features, such as support for an alternate protocol, precoding to prevent contiguous burst errors, and link equalization flow enhancements. While these features offer several advantages, they also pose many additional challenges for verification engineers. This paper discusses the PCIe Gen5 features and their verification challenges. It also describes a case study conducted by Siemens in collaboration with Anritsu on how to address these challenges using a strong verification IP solution.

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