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PCIe 5.0 SerDes Test and Analysis

This paper examines the crucial PCIe 5.0 serializer/deserializer (SerDes) tests.

The key test equipment consists of a bit error ratio tester (BERT) and an oscilloscope. In particular, PCIe 5.0 testing requires an instrument quality BERT pulse pattern generator (PPG) that can apply precise levels of specific signal impairments and a BERT error detector (ED) that can analyze the SerDes output bit error ratio (BER) to determine if it is compliant with the PCIe specifications.

For the most complicated SerDes tests, link equalization training, the BERT must emulate a reference SerDes; the PPG and ED must interact with the device under test (DUT) at the PHY logical sub-block level of the PCIe 5.0 protocol stack. In other words, the BERT must have some protocol awareness. Whether we’re performing transmitter or receiver tests, both roles of the SerDes are involved; to keep the distinction clear, we’ll refer to the DUT-SerDes as DUT-transmitter or DUT-receiver accordingly.

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