March 30, 2022
Anritsu will once again provide thought leadership sessions to help chip, board, and system engineers better understand how to effectively test designs utilizing emerging technologies during DesignCon 2022. A Diamond sponsor of the premier high-speed communications and system design conference, Anritsu will host Test Talks and presentations, as well as participate in a technology panel during the show from April 5-7.
The Test Talks will focus on key technologies engineers must consider when designing high-speed interconnects and systems. They are part of a series of thought leadership initiatives in which Anritsu will participate (figure 1). We will focus on three of them in this post – PAM4, USB Type-C®, and PCIe® 6.0.
Technology Overview – PAM4 is a modulation scheme that combines two bits into a single symbol with four amplitude levels. It allows for the doubling of capacity per lane while leveraging current large-volume, reliable electro-optical components.1
IEEE 802.3 has adopted PAM4, which supports 50 Gbps/lane, as the encoding technology at the physical layer for 400 GbE, 200 GbE, and 50 GbE interfaces. PAM4 has a minimal bandwidth increase and PAM4 introduces a signal-to-noise (SNR) loss. To compensate, forward error correction (FEC) is used.2
Testing – Anritsu Sr. Business Development Manager Hiroshi Goto will discuss PAM4 when he sits on a panel during DesignCon 2022. Held in Ballroom GH at 4:45, April 5, the session, entitled The Case of the Closing Eyes: PAM-N, What Can be Tested?, will detail PHY layer validation techniques that are conclusive enough for widespread, error-free adoption. Attendees will leave the session with a greater understanding of challenges created by the new communications system design methodology, specifically as it relates to semiconductor development and test solutions.
Anritsu will also conduct live demonstrations on April 6. PAM4 bit error rate (BER) and jitter tolerance (JTOL) tests, FEC and burst error analysis, as well as the test capabilities of its Signal Quality Analyzer-R MP1900A BERT. Another live demonstration will feature PCIe® 5.0 receiver LEQ compliance, RX LEQ and JTOL, and TX LEQ response time tests.
Technology Overview – USB Type-C, developed by the USB Implementers’ Forum (USB-IF), can transfer data at up to 10 Gbps – 20 times faster than USB 2.0. It can transfer an entire high-definition feature-length movie in just 30 seconds, as well as deliver full Ultra-HD 4K video resolution to displays.3
More power is another benefit of USB Type-C. With up to 100 watts, or 3 amps of power, USB Type-C cables can charge almost anything, from laptops to large high-resolution monitors.
Testing – Mike Engbretson, Product Manager – High Speed Oscilloscope Solutions, Teledyne LeCroy, will lead a Test Talk session on USB Type-C Standard PHY Testing, where he will discuss the latest PHY transmitter and receiver test methods for USB4™ and DisplayPort™ 2.x, which require USB Type-C connectors. He will also touch on the latest PHY logical layer (PHY-Logic) debug tools for USB Type-C system integration. The session will be held in Mission City Ballroom B5 on April 6.
The ability to accurately conduct these tests is important for emerging high-speed interconnect designs, as Intel’s Thunderbolt PHY specification has been adopted as a “building block” for USB4 and DisplayPort specifications at the physical layer. The highest data rates over the USB Type-C are now 20 Gb/s on each lane for data throughput of 40 Gb/s on two lanes for USB4 and 80 Gb/s over four lanes for DisplayPort 2.0.
Technology Overview – As stated by the PCI-SIG, PCIe 6.0 has a transfer rate of 64 GT/s and up to 256 GB/s via x16 configuration. It doubles the bandwidth and power efficiency of the PCIe 5.0 specification to meet industry demand for a high-speed, low-latency interconnects (figure 2).
The PCIe 6.0 specification introduces PAM4 signaling, low-latency FEC and Flit (Flow Control Unit)-based encoding. The specification also supports data-intensive markets, including data centers, artificial intelligence/machine learning, IoT, and military/aerospace.
Testing – Engineers utilizing PCIe 6.0 in their designs can attend PCIe 6.0 & Beyond: PAM4 Burst BER & Jitter Tolerance Test with FEC Uncorrectable Error Analysis. Hiroshi Goto will focus on PAM4 BER and jitter tolerance tests for SERDES, DSP, and CDR used by transceivers where the pre-FEC evaluation of bit error rate performance is required, as well as correctable/uncorrectable FEC symbol error performance. The presentation is April 7 at 11:15 a.m. in the Great American Meeting Room 1.
Goto will also lead the PAM4 BER & JTOL Test Solution for PCIe 6.0 & Beyond Test Talk on April 6 in the Mission City Ballroom B5. It will focus on 32 Gbaud and above, PAM4 BER tests, and jitter tolerance tests. It will also include FEC and burst errors analysis to provide insight into PCIe 6.0 and 400/800GE applications.
Anritsu will focus on other signal integrity applications and test solutions to meet their specific requirements during DesignCon 2022, as well. One session, Time Domain Reflectometer Application for VNAs, will be held at 2:00 p.m., April 6 in Mission City Ballroom B5. Michael Yang, Senior Product Manager, VNAs, will discuss how to use a vector network analyzer (VNA) to more cost-effectively conduct time domain reflectometer measurements rather than a signal generator and oscilloscope when a fast-rising signal incident occurs.
The Anritsu ShockLine™ ME7868A two-port VNA will be part of demonstrations conducted by RoBAT, Ltd. (booth #1449), as part of the company’s launch of signal integrity test machines at DesignCon 2022. The capability to create a N x N s-parameter matrix with the ShockLine™ VNAs will be part of the demonstration, which will feature RoBAT’s new manual, semi-automatic, and fully automatic test machines.
For a full schedule of the presentations and demonstrations Anritsu is hosting, visit our DesignCon 2022 page.