PCI Express (PCIe) 6.0 is being developed to meet the high-speed data transmission needs of emerging applications, particularly data centers supporting 5G. It features a doubling of data rates and other enhanced performance specs but at a cost of added complexity for high-speed interconnect designs. Engineers designing such equipment must verify performance via real-time analysis, an approach that saves time and improves repeatability.
Read this Design World article to learn about the evolution of PCIe and the specifics of PCIe 6.0 as compared to previous specifications including the integration of PAM4 technology and FLIT encoding. The article also discusses FEC and BER in PCIe 6.0 performance evaluation and provides a recommendation of a BERT test solution with real-time FEC symbol-capture capability that makes for repeatable and high-confidence measurements.