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PCIe 5.0 SerDes Test and Analysis

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www.anritsu.com 1 White paper PCIe 5.0 SerDes Test and Analysis 1. Introduction to PCIe Gen 5 .................................................................................... 2 2. The Challenge of NRZ at 32 GT/s .......................................................................... 3 2.1 Inter-symbol Interference and Equalization .......................................... 4 3. Comparison of PCIe 4.0 and 5.0 SerDes Requirements ..................................... 5 4. Link Training ............................................................................................................ 7 5. Transmitter Link Equalization Test ....................................................................... 9 5.1 Initial Transmitter Equalization Test ....................................................... 9 5.2 Transmitter Link Equalization Response Test ...................................... 10 6. Receiver Link Equalization Test ........................................................................... 11 6.1 Stressed Eye Calibration ......................................................................... 12 6.2 The Receiver Link Equalization BER Test .............................................. 15 6.3 Debugging Receiver Link Equalization ................................................. 16 7. Transmitter PLL Bandwidth Test ......................................................................... 16 8. Receiver Jitter Tolerance Test (JTOL) ................................................................... 19 9. BASE Specification Compliance Testing ............................................................. 20 10. Required Test Equipment Features .................................................................... 21 10.1 Oscilloscope ............................................................................................ 21 10.2 BERT (bit error rate tester) ..................................................................... 21

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