March 12, 2021
Engineers designing and testing differential devices, particularly printed circuit boards (PCBs), rely on vector network analyzers (VNAs) as part of their continual quest to shorten design cycles and improve product time to market. As designs continue to extend to higher frequencies and board space is at a premium certain VNA tools and test techniques gain importance. Sequential peeling is one example.
Network extraction is a design tool used by engineers to identify and remove subsets of a structure (e.g. test fixture, pc board, other interconnect) that behave as localized pseudo-lumped-element reflection centers. Sequential peeling is a model/measurement-based method of network extraction for de-embedding that helps analyze isolated defects within a test fixture or other complex network. The sequential peeling technique acquires detailed information about the fixture making it easy to improve the test fixture design and, ultimately, first-time yields.
Sequential peeling is particularly useful for electrically small structures with isolated vias in the transmission line runs, such as on PCBs. The reason is because sequential peeling identifies time domain elements and then fits a shunt admittance or series impedance model to the isolated data. Once a series of these elements are identified, a more complete composite model of the structure can be obtained and de-embedded.
In this blog, we will outline the sequential peeling process and the insight engineers can gather when designing PCBs.
VNA-based Test Configuration
In the process to be described in this post, an Anritsu ShockLine™ MS46524B 4-port 43.5 GHz VNA with time domain and universal fixture extraction was used. One benefit of the ShockLine family in all environments – including this application – is its advanced Nonlinear Transmission Line (NLTL) technology. The proprietary NLTL architecture features excellent stability and dynamic range for more detailed and accurate measurements.
The example is based on testing a pcb trace on a demo board from Wildriver Technology (CMP-28 with 2.4 mm connectors) with four vias. A three-step process is used:
- A K-V adaptor is connected on each test cable
- A full two-port SOLT calibration is performed by the 3654D V calibration kit on a ShockLine MS46524B using the V(F)-V(F) (34733) barrel with 24.15 mm as a thru
- The VNA frequency sweep is from 50 MHz – 40 GHz with 800 points
If an engineer looks at the initial time domain representation (Tr3 as shown in the second plot in Figure 1) from the measurement, he/she can see the first via appearing near 76.22 ps. The frequency domain response shows a complex standing wave pattern due to all of the reflection centers and a worst-case reflection coefficient of about -1.6 dB.
In the example, the peeling process was initiated with a series-Z defect model selection, since the defect was known to be inductive. The 76.22 ps location was entered. While this choice appears to be clearly dominant, 0 could have been entered to trigger the auto-selection routine. The resulting .s2p file and lead-in transmission line was de-embedded.
A few elements need to be noted. In particular, the saved .s2p files do not include positional information. It is important to move the reference plane to the defect. Figure 3 is an example, as the reference plane is moved to 22.8 mm (air equivalent length of 76.22 ps) location. The .s2p file characterizes the reflection center.
If de-embedding is applied, the responses seen will appear as live traces, with the original data stored in memory. The frequency domain reflection peaks drop by at least 7 dB and the initial time domain impulse response is suppressed.
Impact of De-embedding
De-embedding was applied and the frequency domain responses for all three configurations (original structure, with first peeling step de-embedded, with both first and second steps de-embedded) are shown in Figures 5 and 6. The main reflection peaks have been heavily suppressed (in Figure 5, the blue curve on both Tr1 in the upper plot and Tr3 in the lower plot), as some dominant reflection centers are de-embedded. Figure 6 indicates that the vias have been de-embedded after the sequential peeling method.
The value of other responses increases, because the reflections deeper in the structure are interacting with the launch reflection. The result is altered frequency distribution. Plus, the extraction is not perfect because the vias likely have some distributed characteristics. Therefore, they cannot be completely described by the simple series-Z model used in this demonstration. For fixtures with very distributed reflection centers, the peeling method is less successful. Finally, the impedance measurement after peeling clearly shows the impedance for the vias has been de-embedded.
Sequential Peeling Effectiveness
As shown by this example, the sequential peeling network extraction tool is an effective and simple solution to de-embed subsets of a structure that behave as localized pseudo-lumped-element reflection centers. This is particularly relevant for electrically small structures – such as on-wafer interconnects – with runs of transmission line punctuated by electrically small structures. PCBs with isolated vias or studs in transmission lines are a prime example. One final note is that this process is based on reflection measurements; it does not work well with insertion loss measurements.
To learn more, you can download an application note entitled Performing Sequential Peeling Extraction and De-embedding with an Anritsu ShockLine Vector Network Analyzer.